1. Technical Field
The present disclosure relates to the field of electrical circuits. The present disclosure relates more particularly to current mirror circuits driving a load.
2. Description of the Related Art
Current mirror circuits are used in many applications to supply a controlled current to a load. A typical current mirror includes a current source that passes a selected current through a diode connected transistor. A voltage is forced on the gate of the transistor according to the current flowing through the transistor. The current source therefore biases the gate of the transistor according to the current being forced through the transistor. The gate voltage from the transistor is then supplied to the gate of the second transistor. Typically the sources of the two transistors are connected to the same voltage, thereby causing the current flowing through the second transistor to be the same as or a scalar factor of the current flowing through the first transistor, according to the width to length ratios of the transistors.
FIG. 1 illustrates a prior art current mirror circuit 20 used to drive a current through a load. The current mirror circuit 20 includes a current source I1 driving a bias current through PMOS channel transistor T1. The source of the high transistor T1 is connected to the voltage VDD. The gate of transistor T1 is connected to the drain of transistor T1.
When a transistor is in saturation mode, the current flowing through the transistor depends largely on the voltage difference between the gate and the source of the transistor. As the difference between the gate and the source voltage increases, the current flowing through the transistor increases. Because the gate of transistor T1 is coupled to the drain of transistor T1, the voltage at the drain of transistor T1 will be the voltage relative to VDD which will cause a drain current in T1 equal to the bias current driven by current source I1.
The current mirror circuit 20 includes a transistor T2, the source of which is coupled to VDD and whose gate is coupled to the gate of transistor T1. The gate to source voltage of transistor T2 is therefore the same as the gate to source voltage of transistor T1. The current flowing through transistor T2 will therefore mirror the current flowing through transistor T1. A load is coupled between the drain of transistor T2 and ground voltage GND.
In this configuration the current supplied to the load is controlled by the current source I1 and transistor T1. This is so a steady current can be supplied to the load regardless of the resistance of the load. If the resistance of the load changes, the current being supplied to the load will remain the same.
Problems can arise, however, when there are fluctuations in the supply voltage VDD. While the current flowing through the load may be stable in spite of changes in the load resistance, changes in the supply voltage VDD can alter the current flowing through to the load. Fluctuations in the supply voltage introduce noise into the circuit, and thus cause noise in the load current. For some types of loads, any noise in the load current can be very undesirable and can have negative effects on the function of the load.
Efforts have been made to improve the power supply rejection ratio (PSR) of current mirror circuits driving a load in order to make the load current tolerant to power supply variation. In other words, efforts have been made to have the load current be highly insensitive to variations in supply voltages.
One way to improve PSR is to increase the output resistance r0 of the load transistor T2. In the circuit 20 of FIG. 1, this can only be done by increasing the channel length L of transistor T2.
A second method for increasing the output resistance r02 of the load transistor T2 is to introduce a cascode amplifier in the load current path. FIG. 2 illustrates a current mirror circuit 20 including a cascode amplifier formed from transistors T2 and T3. Transistor T3 is coupled between the load and transistor T2. The gate of transistor T3 is coupled to the gate of transistor T4. Transistor T4 is biased by current source I2. The current source I2 is controlled by the current source I1. This configuration increases the output resistance r02 by a factor of the gain of the cascode amplifier. While the current mirror circuit 20 of FIG. 2 effectively improves the output resistance and the PSR, higher power supply voltages may be required to ensure operability of the circuit 20.
FIG. 3 illustrates a current mirror circuit 20 including a regulated cascode current mirror. The regulated cascode current mirror includes an amplifier 24 having a non-inverting input coupled to the source of transistor T3 and an inverting input coupled to a reference voltage Vref. The reference voltage Vref is VDD referred. The current mirror circuit 20 of FIG. 3 further increases the output resistance r02 and the PSR. In particular the output resistance r02 is further increased by the gain of the amplifier 24. The gain of the amplifier 24 can be very high, greatly increasing the output resistance r02.
However, the regulated cascode circuit of FIG. 3 includes increased voltage demands and can't be designed to work at lower voltages. Higher supply voltages may be required than even those of the cascode current mirror circuit of FIG. 2.
Another method for improving PSR is the bootstrap current mirror, which, instead of increasing output resistance at the cost of supply voltage, increases the output resistance at the cost of device stability. The output resistance is increased at the cost of increased current consumption. If current consumption needs to be reduced, the phase noise will get worse in the case of a Voltage Controlled Oscillator.